The present invention relates to a voltage-controlled delay line, a voltage-controlled oscillator with direct phase control, a clock/data recovery circuit, and a clock/data recovery apparatus suitable for use in an integrated circuit.
In the past, analog phase-locked loop (PLL) technology has been used to recover a clock signal from a received data signal. The recovered clock signal is generated by a voltage-controlled oscillator (VCO), and is synchronized with the data signal by comparing the phases of the clock signal and data signal, the phase of the data signal being indicated by transitions in the data value. A problem with this technique is that synchronization may be lost if there are no data transitions for an extended time.
In recent years, analog technology has been combined with digital technology to create clock recovery circuits that overcome this problem. In one type of circuit, an analog PLL locked to a stable system reference clock is used to generate a multiple-phase clock signal. Digital circuitry then selects one of the multiple phases that correctly samples the received data signal.
In apparatus receiving data on two or more channels in parallel, the same multiple-phase clock signal can in theory be shared, the appropriate phase being selected for each channel separately. Unfortunately, supplying a multiple-phase clock to many different receiving circuits requires much interconnection wiring, because each phase of the multiple-phase clock is a separate signal. In an integrated circuit, the large number of clock signal lines can create layout and routing problems. Moreover, it is not easy to maintain the correct phase relationships among the different clock phases. Some channels may consequently be supplied with badly skewed multiple-phase clock signals, and experience problems in receiving data correctly.